This paper presents a counter design based on multiple LFSR stages that retains the advantages of a single-stage LFSR but only requires decoding logic that scales logarithmically with the number of stages rather than exponentially with the number of bits as required by other methods. However, significant logic is required to decode the count order into binary, causing system-on-chip designs to be unfeasible. N2 - Linear-feedback shift register (LFSR) counters have been shown to be well suited to applications requiring large arrays of counters and can improve the area and performance compared with conventional binary counters. T1 - Multistage linear feedback shift register counters with reduced decoding logic in 130-nm CMOS for large-scale array applications
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